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Bespoke mixed signal ASIC design costs down

In this article for Electronics Weekly, SWINDON’s Sales Director Richard Mount describes how the cost for bespoke mixed signal design and production has been able to fall dramatically over the last few years.

Contrary to popular belief, the cost of a custom analogue or mixed-signal silicon design has fallen dramatically in recent years. This now allows even more companies to consider developing their own device, customised to their project requirements and usually encapsulating their intellectual property in a more secure, high performance device.

Digital ASIC development at the leading edge of process technology is an expensive business, with masks costing millions of dollars. This has led many people to think that they can’t afford to design their own device, but for analogue and mixed signal designs, the 0.35micron and 0.18micron process nodes are now fully mature and can be very cost effective.

Added value is in the design skills of the engineer

These are still cutting edge designs but the added value is in the design skills of the engineer, rather than in squeezing the last picosecond of clock speed out of the device. Custom designs are also increasingly popular for replacing obsolete parts, and this type of project can extend product lifetime at low cost, especially as the new version can be made pin-for-pin compatible with the old device.

However, there are issues with analogue and mixed-signal designs that mean having all the elements under one roof avoids the problems that can make projects prohibitively expensive and high risk. While there are readily available analogue and mixed-signal design tools, increasingly there are other elements of the design to consider that can be expensive if using a pureplay foundry, standalone design and external test houses.

Elements of the design that can be expensive

The foundry element

While a foundry may have several process technologies to offer, it may not offer the right combination of technology – from CMOS to BiCMOS or SiGe – at the right geometries. This can lead to design trade-offs at the start. Then there are the other IP blocks that will be used, usually for the interfaces and analogue-to-digital converters (ADCs) and digital-to analogue converters (DACs).

The design element

Designing your own ADC, DAC or serial interface is possible, but time consuming to verify and test, and there are plenty of IP blocks available on the market – the foundry will have a set optimised for its processes. Finding the right blocks, negotiating the rights, making sure the IP is appropriate for the process technology all takes time that detracts from the focus on the core of the project and may require trade-offs that will limit the performance that the project requires.

Having to use a different process just because an interface block is not available in the chosen, optimum process doesn’t make sense, so having IP blocks available, optimised for various process technologies, is a key requirement.

Often there is a mismatch between the functional verification of a design, perhaps running on an FPGA with certain peripherals, and the translation to a custom device with a different, though functionally equivalent, set of interfaces. Being able to square that circle and ensure that the design does what the engineer intended takes experience and knowledge. This also ties into the test and assurance which are also linked to the design and to the process technology.

Using a foundry, perhaps with the design running on a low cost multi-project wafer (MPW) with other customers, can seem to be a cost effective approach. However, these devices need to be packaged and tested, and that’s where the costs can unexpectedly rocket.

The testing element

Testing the analogue elements of a chip is not a trivial task and many of the test houses associated with the foundries may not be up to the job, and as a designer you have little control over the test coverage and the final yield. Suddenly the cost and time taken for testing becomes a major headache as does quality assurance. Having wafer probing and ATE testing that is closely coupled with the test vectors used for the verification of the design on a particular process with the right design rules is not easy to achieve unless it is all under one roof, and bringing all this together takes significant amounts of management and experience.

Once the ASIC has been tested, it needs packaging. While the major packaging houses have subsidiaries here in Europe, they may not have the specialist materials or qualification processes that many analogue and mixed signal designs require, especially for replacing obsolete parts in industrial or military equipment. Having the wafer test and final test available at a single site also dramatically simplifies the traceability of the product, another key requirement in many quality systems.

Bringing all the elements together

Bringing all the elements of an analogue or mixed-signal Asic design under one roof allows the cost of each step of the process to be contained effectively. Managing each step of the design, manufacturing and test of the device with separate partners is time-consuming and can lead to large unexpected costs when problems arise on the other side of the world. Combining these elements with flexibility in the choice of process technology and experience in chip design means design and manufacturing issues can be quickly and cost effectively resolved.

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SWINDON Silicon Systems Limited

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