ASIC Design and Development
Swindon’s team of ASIC designers, utilising our own IP library from production proven former designs and supplemented by the digital block IP libraries of its foundry partners, form the base for a predictable development plan.
In all ASICs, where market leadership is the aim, there will be a requirement for custom circuits in order to provide that competitive edge. Swindon has a depth of engineering talent that ensures that all aspects of the design can be met in-house. This ensures that the customer will still meet the critical time-to-market but also benefit from a unique solution and product.
The ASIC development phase includes:
Mixed signal - Corner simulations and verifications
- Custom layout
- Synthesis of all digital sections
- Top level integration, layout and verification
- Design documentation
- Final wafer probe and ATE production test programmes
- Qualification plan
- Design Tape Out procedure
Foundry Process
Swindon combines its own expertise with that of the world’s leading
Foundry Process Information
| Name | Process Description | Core(V) | I|O | MV|HV(V) | OPTO | NVM |
|---|---|---|---|---|---|---|
| 55/65nm | Flexibile analog mixed-signal | 1.2|1.8|2.5 | 3.3|5|8|12 | eFlash | ||
| 0.13µm | High flexibility analog mixed-signal | 1.5 | 3.3 | |||
| 0.18µm | High performance mixed signal, high temperature, high-voltage and NVM | 1.8 | 3.3 | 6|10|15|20|40| 45 | TrimOTP eFlash NVRAM |
|
| 0.18µm | High performance analog mixed signal | 1.8 | 3.3 5.0 | TrimOTP PolyFuse |
||
| 0.18µm | Power Management | 1.8 5.0 | 5.0 | 13|15|25|30|40| 45|60 | TrimOTP PolyFuse EEPROM eFlash |
|
| 0.18µm | Image Sensor Enabled | 3.3 | 1.8 3.3 | TrimOTP PolyFuse |
||
| 0.25µm | Analog/digital mixed signal baseline | 2.5 | 3.3 5.0 | eFlash | ||
| 0.35µm | High performance, high voltage | 3.3 | 3.3 5.0 | 12|14|18|45|55| 75|100 | TrimOTP ZenerZap HD OTP NV Latch EEPROM CEEPROM |
|
| 0.35µm | High temperature analog mixed signal | 3.3 | 3.3 5.0 | 12|14|18|45|55| 75|100 | TrimOTP ZenerZap EEPROM CEEPROM |
|
| 0.35µm | High speed opto | 3.3 | 3.3 5.0 | 12 | PolyFuse ZenerZap |
|
| 0.35µm | Ultra-High-Voltage | 5.0 | 5.0 | 20|40|700 | ZenerZap |
Memory Options
| Memory Options | Typical Size | Data Retention | Endurance |
|---|---|---|---|
| SRAM | 64-512kbits | ||
| Trim Registers | |||
| Bit Writeable OTP | 1 - 128 bits | 10 Years @ 85˚C | 10k Cycles |
| Bit R/W | 1 - 128bits | ||
| Word Writeable OTP | 8bit - 2kbit | ||
| Application Memory | |||
| OTP | 1kbit, 64kbit, 256kbit | 10 Years @ 85˚C | 1k Cycles @ 85˚C |
| EEPROM | 32bit – 32kbit | 10 Years @ 125˚C | 100k Cycles |
| CEEPROM (Fast access and lower power) | 32bit – 4kbit | 10 Years @ 125˚C | 100k Cycles |
| FLASH | 32kbit – 1Mbit | 20 Years @ 85˚C | 1k Cycles @ 85˚C |
| NVRAM | 1kbit – 16kbit | 10 Years @ 125˚C | 10k Cycles |
Custom IC Builder
IC Builder is a new way for designers to visualise what their mixed signal ASIC and MEMS solution may look like for their application.
Click by click, progressively add the functions required for your intelligent sensing application and see what your resulting package could look like.
