Custom ASIC Design
Swindon Silicon Systems – Your custom ASIC design partner
For many years, integrated circuits (IC) were standardized chips that supported a multitude of applications. However by the late 1960’s, through technological advancements such gate arrays, custom Application Specific Integrated Circuits (ASIC) were born. Over the years, custom ASIC demand grew as companies wanted to differentiate themselves from their competition, both technically and commercially. This is never more true than today as automation and the Internet of Things (IoT) continue to accelerate the use of custom ICs, driven by specific hardware requirements from companies striving to take the market lead.
There are many defining reasons why product developers design a custom ASIC into their product. ASICs are custom solutions that encompasses optimised high functionality and performance with an efficient use of power and space for a specified application and market.
Some of the valuable benefits of using Custom ASIC technology are:
- Optimised performance
- Footprint reduction
- Lower power consumption
- Intellectual Property (IP) protection
- Non obsolescence assurances and options
- Product manufacturing efficiencies
- Improved reliability
As technology companies continue to explore means and ways to differentiate their product whilst also harnessing the universe of interconnected devices, the ASIC will remain at the forefront of delivering this promise. But the industry is changing, and the development and realisation of these ASICs are also changing.
With the ever-increasing evolution of the automobile, the Internet of Things, sensors and electrification, to name but a few, the need to protect intellectual property, avoid supply chain delays, avoid obsolescence and deliver ever increasing competitive differentiation, the demand on semiconductor (foundry and fabless) suppliers is on an upward trajectory.
What is a custom ASIC and what can be customised?
ASICs are chips designed for a customer’s specific application, including hardware and software, which is specifically designed to the customer’s specification and supplied only to them.
The ASIC will be designed using as many IP library blocks that the ASIC designer can use, along with any foundry or third party IP.
It is however important to remember that every system block and parameter of the ASIC can be customized, depending upon the development budget and time allowed, but this is rarely required.
If we use a sensor interface as an application example, the following list highlights some, but not all, of the commonly customised areas that are requested in order to provide our customer’s with a custom ASIC that delivers product leadership, differentiation or solutions that cannot be found in a commercial off the shelf (COTS) chip.
- LNA noise figure
- ADC performance – number of bits and sampling rate.
- Number of channels
- Digital processing – simple or more complex
- Memory – how much and what type
- Input source compatibility – inductive, resistive, capacitive, magnetic and optical, for example.
- Communications protocols – either wired or wireless
- Form fit of the silicon
- Packaging – bare die, flip chip or packaged
- Temperature range
- Industry qualification – AEC Q100 for example.
- Function safety requirements.
If an engineering team is developing a product that requires higher integration but they cannot find a solution using COTS, the first step is to look at using custom ASIC technology and finding a suitably experienced partner for their market and application.
Before commencing any custom ASIC development program, both the custom ASIC designer and the customer will need to understand what the project objectives are. From this there are certain areas of the project that can be defined in order that a full project plan and costing can be costed.
- Project objectives – custom ASIC requirements both technically and commercially.
- Feasibility – Can the objectives be met?
- Resourcing – are the required personnel, tools and material available?
- Technology – what is the optimal process node to achieve the objectives?
- Chip partitioning – what topology is to be targeted – ASIC, SoC or SiP?